There is a need in reading information from an optical disk which is to provide correction of distorted mark and land lengths. A systematic error is that which affects all consecutive mark edge positions in a predictable way over some period of time, generally greater than two bytes. In an optical recording system, systematic error is caused by the following: focus and tracking errors, write power error, media sensitivity variation, optical aberrations, and stamper imperfections in the case of etched or molded media. Systematic mark length error is a problem because it limits the data capacity and reliability that can be achieved for a given system.
The current state of the art uses multiple phase locked loops (PLLs) or a single phase locked loop as a data edge position reference for detecting length errors. Reference is made to assigned U.S. Pat. No. 4,734,900 granted Mar. 29, 1988 to IBM entitled "Restoring And Clocking Pulse Width Modulated Data."
The basis of a PLL data correction circuit is to monitor the timing difference between the played back data edges, and the previously synchronized data clock generated by the PLL. The detected timing difference or "error" is then fed back into the circuit to provide a way for changing the data edge positions. Conventionally, the PLL positions the clock edges to equalize the timing difference between the leading data edge and clock edge and the trailing data edge and clock edge. This relationship can be used to measure systematic error in the length of the data. When there is a length error, the leading and trailing data edges are offset in equal and opposite directions relative to the clock edges. The direction and length of the error can be determined by the relative position of the data edges (leading or trailing) to the clock edges. A duty cycle correction circuit measures these data and clock edge position differences and feeds the correction back into the data channel in either open or closed loop configurations. The maintenance of ideal edge positions i.e. when clock and data edges are superimposed, provide maximum margin for any single edge to leave the detection window causing a bit error. As a result, the number of bit errors produced by the system is minimized.
There are three fundamental correction techniques outlined in the IBM patent. In this patent, the first is a dual phase locked loop approach wherein a first phase lock loop PLL A is locked to the leading edges of the pulse length modulated data, and a second phase lock loop PLL B is locked to the trailing edges of the data. An error signal is then generated by monitoring the phase difference between the two clock signals generated by the PLL's A and B. The problems with a multiple phase lock loop (PLL) approach are complexity, and opportunity for interactions between the loops causing oscillations. A second technique described employs a single PLL, however, it utilizes two one shot multivibrators to provide the corrected data signal, one fixed and one variable. The problem with this solution is that "one shots" are very unstable devices where response varies greatly with temperature and component variations making the solution unstable and inconsistent. A second problem with this approach is that only one edge is being shifted relative to the clock forcing the PLL to adjust as the data lengths are being corrected. If two `one shots` were used, one per edge, the variation in response of each `one shot` with respect to the other could result in very different leading and trailing edge position responses to timing errors. This solution can lead to residual length errors, instability and interaction when submitted to certain disturbances. Correction bandwidth will be limited to PLL response. A third technique described uses a very high speed clock and counter to monitor the data edge position relative to the system clock edge to generate an error signal. This system has the problem of requiring a very high frequency clock, on the order of fifty times the data rate. Clock frequencies of this order will cause electromagnetic interference (EMI) and other problems that would be extremely difficult and costly to contain in a computer peripheral environment.